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datasheet 1 to 4 hcsl clock buffer ics557-06 idt? / ics? 1 to 4 hcsl clock buffer 1 ics557-06 rev f 090407 description the ics557-06 is a one to four differential clock buffer designed for use in pci-express applications. the device selects one of the two differential hcsl or lvds input pairs and fans out to four pairs of differential hcsl or lvds outputs. features ? packaged in 20-pin tssop ? available in pb (lead) free package ? operating voltage of 3.3 v ? low power consumption ? input differential clock of up to 200 mhz for hcsl and up to 100 mhz for lvds ? jitter 60 ps (cycle-to-cycle) ? output-to-output skew of 50 ps ? available in industrial temperature range (-40 to +85c) block diagram vdd clka clka rr (iref) clkb clkb clkc clkc clkd clkd sel gnd in1 in1 in2 in2 mux 2 to 1 oe 2 2 pd
ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer idt? / ics? 1 to 4 hcsl clock buffer 2 ics557-06 rev f 090407 pin assignment select table pin descriptions 13 4 12 5 11 in2 8 9 10 gnd oe clkc clkd gnd clkd 17 16 iref 3 in1 in1 clkb 18 clkb 1 sel vddin clka 20 clka 19 14 2 7 in2 pd vdd clkc 15 6 20-pin (173 mil) tssop sel input pair selected 0in2/ in2 1in1/ in1 pin pin name pin type pin description 1 sel input sel=1 selects in1/in1 . sel =0 selects in2/ in2 . internal pull-up resistor. 2 vddin power connect to +3.3 v. supply voltage for input clocks. 3 in1 input hcsl/lvds true input signal 1. 4 in1 input hcsl/lvds complimentary input signal 1. 5 pd input powers down the chip and tri-states outputs when low. internal pull-up 6 in2 input hcsl/lvds true input signal 2. 7 in2 input hcsl/lvds complimentary input signal 2. 8 oe input provides fast output on, tri-states output (high = enable outputs; low = disable). internal pull-up resistor outputs. 9 gnd power connect to ground. 10 rr(iref) output precision resistor attached to this pin is connected to the internal current 11 clkd output differential comp limentary output clock d. 12 clkd output differential true output clock d. 13 clkc output differential comp limentary output clock c. 14 clkc output differential true output clock c. 15 vddout power connect to +3.3 v. supply voltage for output clocks. 16 gnd power connect to ground. 17 clkb output differential complimentary output clock b. 18 clkb output differential true output clock b. 19 clka output differential complimentary output clock a. 20 clka output differential true output clock a.
ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer idt? / ics? 1 to 4 hcsl clock buffer 3 ics557-06 rev f 090407 application information decoupling capacitors as with any high-performance mixed-signal ic, the ics557-06 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guide lines should be observed. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). other signal traces should be routed away from the ics557-06. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. external components a minimum number of external components are required for proper operation. decoupling capacitors of 0.01 f should be connected between vdd and gnd pairs (2,9 and 15,16) as close to the device as possible. current reference source r r (iref) if board target trace impedance (z) is 50 ? , then rr = 475 ? (1%), providing iref of 2.32 ma, output current (i oh ) is equal to 6*iref. load resistors r l since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. output termination the pci-express differential clock outputs of the ics557-06 are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are shown in detail in the pci-express layout guidelines section. the ics557-06 can also be configured for lvds compatible voltage levels. see the lvds compatible layout guidelines section.
ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer idt? / ics? 1 to 4 hcsl clock buffer 4 ics557-06 rev f 090407 output structures general pcb layout recommendations for optimum device performance and lowest output phase noise, the following guide lines should be observed. 1. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias should be used between decoupling capacitor and vdd pin. 3. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces should be routed away from the ics557-06.this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. r r 475 6*iref =2.3 ma iref see output termination sections - pages 3 ~ 5 w
ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer idt? / ics? 1 to 4 hcsl clock buffer 5 ics557-06 rev f 090407 pci-express layout guidelines pci-express device routing typical pci-express (hcsl) waveform common recommendations for differential routing dimension or value unit l1 length, route as non-coupled 50 ohm trace. 0.5 max inch l2 length, route as non-coupled 50 ohm trace. 0.2 max inch l3 length, route as non-coupled 50 ohm trace. 0.2 max inch r s 33 ohm r t 49.9 ohm differential routing on a single pcb dimension or value unit l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch differential routing to a pci express connector dimension or value unit l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch r s r s r t r t pci-express load or connector l1 l2 l3? l4 l1? l2? l3 l4? ics557-06 output clock 0.175 v 0.52 v 0.175 v 0.52 v t or t of 500 ps 500 ps 700 mv 0
ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer idt? / ics? 1 to 4 hcsl clock buffer 6 ics557-06 rev f 090407 lvds compatible layout guidelines lvds device routing typical lvds waveform lvds recommendations for differential routing dimension or value unit l1 length, route as non-coupled 50 ohm trace. 0.5 max inch l2 length, route as non-coupled 50 ohm trace. 0.2 max inch r p 100 ohm r q 100 ohm r t 150 ohm l3 length, route as coupled 50 ohm differential trace. l3 length, route as coupled 50 ohm differential trace. l1 l2? l3 l1? l2 l3? r q r p lvds device load ics557-06 clock output r t r t 1150 mv 1250 mv t or t of 500 ps 500 ps 1325 mv 1000 mv 1150 mv 1250 mv
ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer idt? / ics? 1 to 4 hcsl clock buffer 7 ics557-06 rev f 090407 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics557-06. these ratings are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specificat ions is not implied. exposure to ab solute maximum rating conditions for extended periods can affect product reliability. electrical parameters are gua ranteed only over the recommended operating temperature range. dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c 1. single edge is monotonic when transitioning through region. 2. inputs with pull-ups/-downs are not included. item rating supply voltage, vdd, vdda 5.5 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c esd protection (input) 2000 v min. (hbm) parameter symbol conditions min. typ. max. units supply voltage v 3.135 3.465 input high voltage 1 v ih oe, sel, pd 2.0 vdd +0.3 v input low voltage 1 v il oe, sel, pd vss-0.3 0.8 v input leakage current 2 i il 0 < vin < vdd -5 5 a operating supply current i dd 50 ? , 2pf 55 ma i ddoe oe =low 20 ma i ddpd no load, pd =low 400 a input capacitance c in input pin capacitance 7 pf output capacitance c out output pin capacitance 6 pf pin inductance l pin 5nh output resistance r out clk outputs 3.0 k ? pull-up resistor r pup sel, oe, pd 110 k ?
ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer idt? / ics? 1 to 4 hcsl clock buffer 8 ics557-06 rev f 090407 ac electrical characteri stics - clkouta/clkoutb unless stated otherwise, vdd=3.3 v 5% , ambient temperature -40 to +85 c 1 test setup is r l =50 ohms with 2 pf, rr = 475 ? (1%). 2 measurement taken from a single-ended waveform. 3 measurement taken from a differential waveform. 4 measured at the crossing point where instantaneous voltages of both clkout and clkout are equal. 5 clkout pins are tri-stated when oe is low asserted. cl kout is driven differential when oe is high unless its pd = low. parameter symbol conditions min. typ. max. units input frequency 200 mhz output frequency hcsl termination 200 mhz lvds termination 100 input high voltage 1,2 v ih hcsl 660 700 850 mv input low voltage 1,2 v il hcsl -150 0 mv differential input voltages (v id ) lvds 250 350 450 mv input offset voltage (v is ) lvds 1.125 1.25 1.375 v output high voltage 1,2 v oh hcsl 660 700 850 mv output low voltage 1,2 v ol hcsl -150 0 27 mv crossing point voltage 1,2 absolute 250 350 550 mv crossing point voltage 1,2,4 variation over all edges 140 mv jitter, cycle-to-cycle 1,3 60 ps rise time 1,2 t or from 0.175 v to 0.525 v 175 332 700 ps fall time 1,2 t of from 0.525 v to 0.175 v 175 344 700 ps rise/fall time variation 1,2 125 ps skew between outputs measured at crossing point 50 ps duty cycle 1,3 45 55 % output enable time 5 all outputs 10 us output disable time 5 all outputs 10 us input to output delay input differential clock to output differential clock delay measured at mid point of input levels to mid pint of output levels 3ns
ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer idt? / ics? 1 to 4 hcsl clock buffer 9 ics557-06 rev f 090407 thermal characteristics marking diagrams (ics557g-06) (ics557g-06lf) (ics557gi-06lf) notes: 1. ###### is the lot code. 2. yyww is the last two digits of the year, and the week number that the part was assembled. 3. ?lf? denotes pb free package. 4. bottom marking: (origin). origin = country of origin if not usa. parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 93 c/w ja 1 m/s air flow 78 c/w ja 3 m/s air flow 65 c/w thermal resistance junction to case jc 20 c/w 10 20 11 ###### yyww 557g-06 ics 1 10 20 11 ###### yyww 557g06lf ics 1 10 20 11 ###### yyww 557gi06lf ics 1
ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer idt? / ics? 1 to 4 hcsl clock buffer 10 ics557-06 rev f 090407 package outline and package dimensions (20-pin tssop, 173 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both ac curacy and reliability, integrated device technologu (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature ics557g-06 see page 9 tubes 20-pin tssop 0 to +70 c ics557g-06t tape and reel 20-pin tssop 0 to +70 c ics557g-06lf tubes 20-pin tssop 0 to +70 c ics557g-06lft tape and reel 20-pin tssop 0 to +70 c ics557gi-06lf tubes 20-pin tssop -40 to +85 c ICS557GI-06LFT tape and reel 20-pin tssop -40 to +85 c index area 1 2 20 d e1 e seating plane a1 a a2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a1.200.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 6.40 6.60 0.252 0.260 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 a0 8 0 8 aaa -- 0.10 -- 0.004
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-4522 www.idt/go/clockhelp innovate with idt and accelerate your future netw orks. contact: www.idt.com ics557-06 1 to 4 hcsl clock buffer pcie fan out buffer

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